Soft error rate (SER) measures how often, when a memory device is accessed, incorrect data is provided due to external radiation, such as alpha particles or cosmic rays, which can penetrate and upset the operation of the memory device. SER is becoming a more stringent problem as device geometries continue to be reduced, making the devices more susceptible to such phenomena. This issue is even worse for SRAM devices since the storage node capacitance is much smaller for SRAM devices as compared with DRAM devices, which have a relatively large storage capacitor in each bit. Due to their fast operation, SRAM devices still prevail in many high speed applications such as networking, communications, and the like.
Several ways have been proposed to deal with SER issues. Generally, these can be categorized into two groups: (i) adding a capacitor to the storage node to enlarge the critical charge (Qcrit) of the device and make it harder to flip the state of the device; and (ii) reducing the storage node's collecting efficiency of minority carriers, so that flipping the state of the device becomes more difficult. While some of these prior art strategies are successful in reducing the SER numbers, they typically require extra masks and process steps that can reduce overall yield. This makes these strategies expensive to implement. Additionally, some of these strategies are of limited effect in reducing the SER numbers, and are inadequate for advanced technologies.
For these reasons, it would be desirable to provide a new and improved semiconductor memory device having reduced susceptibility to SER and a method for fabricating such a device.